q 45ns and 55ns maximum address access time q Asynchronous operation for compatibility with industrystandard 4K x 8/9 dual-port static RAM www.DataSheet4U.com q CMOS comp.

that require depth expansion, the BUSY pin is open-collector allowing for wired OR circuit configuration. An M/S pin is .

3 The UT7C138/139 consists of an array of 4K words of 8 or 9 bits of dual-port SRAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To hand.

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